Attention

This version of the SDK has been superseded by the latest release of the SDK.

Specs and Features of the AMD AMA Video SDK

The AMD AMA Video SDK

The AMD AMA Video SDK is a complete software stack allowing users to seamlessly leverage the features of AMD video acceleration units such as MA35D. It includes the following elements:

  • Pre-compiled versions of FFmpeg and GStreamer which integrate key video transcoding plug-ins, enabling simple hardware offloading of compute-intensive workloads using these two popular frameworks. These custom versions of FFmpeg and GStreamer link to a host driver which communicates with the hardware on the PCIe card. No hardware experience is required to run FFmpeg or GStreamer commands with the AMD AMA Video SDK.

  • The Xilinx Resource Manager (XRM) which is the software used to manage and allocate all the hardware-accelerated features available in the system. XRM allows running multiple video processing jobs across multiple devices and multiple AMD video acceleration cards.

  • A C-based application programming interface (API) which facilitates the integration of AMD video transcoding capabilities in proprietary frameworks. This API is provided in the form plugins which can be called from external application using the Xilinx Media Accelerator (XMA) interface.

  • A suite of card management tools used to perform actions such as programming, resetting, or querying the status of AMD video acceleration cards.

  • Many examples and tutorials illustrating how to use and make the most of the AMD AMA Video SDK.

MA35D Pipeline

The AMD MA35D Card

The MA35D, which is compatible with AMD AMA Video SDK, is a low-profile, PCI™-based media accelerator card that delivers a high-density real-time transcoding solution for live streaming video service providers, OEMs, and Content Delivery Network (CDNs).

The MA35D card is targeted for both real-time and faster than real-time video workloads. It is expected that one or more sources of video input, either from files or from live video streams, are fed into the transcode pipeline. The encoder encodes one or more output streams from each scaled rendition of the input.

Video Codec Unit

The MA35D accelerator card has 2 VPUs, where each VPU is made of 2 video processing slices. These slices in turn are made of specialized decode, scale, GPU, ML, look ahead, and encode units.

MA35D VPU

Video Codec Unit (VCU) cores are capable of:

  • Video format: YCbCr 4:2:0, 8 or 10-bit per color channel

  • Multi-standard encoding/decoding support, including:

    • ISO MPEG-4 Part 10: Advanced Video Coding (AVC)/ITU H.264 - Baseline, Constrained Baseline, High, High-10, High-10-Intra up to Level 5.2

    • ISO MPEG-H Part 2: High Efficiency Video Coding (HEVC)/ITU H.265 - Main, Main-Intra, Main10, Main-10-Intra, up to Level 5.2

    • AOM AV1: AOMedia Video 1 - Main, High up to Level 5.3

  • Supports resolutions from 128x128 to 3840x2160 portrait and landscape

  • Simultaneous transcoding with a maximum aggregated bandwidth of 4x 4Kp60 per card for AVC or HEVC and 8x 4Kp60 for AV1

  • Look-ahead driven video quality improvements through temporal adaptive and spatial adaptive quantization

  • Low latency rate control

  • Flexible rate control: CBR, VBR, CVBR, and Constant QP

  • Progressive support for H.264, H.265 and AV1

  • HDR10/10+: HDR data is automatically populated by the decoder and passed to other accelerators in the transcode pipeline.

    • The following HDR10 SEI are supported:

      • Mastering Display Color Volume (SEI ITU)

      • Content Light Level (SEI ITU)

      • Alternative Transfer Charateristics (SEI ITU)

    • The following HDR10+ SEI are supported:

      • ST2094_10 (DolbyVision, User defined SEI)

      • ST2094_40 (Samsung, User defined SEI)

    • Behavior for HDR10/10+ SEI is as follows:

      • Static HDR SEI (MDCV, CLL & ATC) will not change in-between IDRs (and even in the video sequence according the HDR standards).

      • MDCV, CLL & ATC will be written only on IDRs, according to the persistency of MDCV, CLL & ATC SEIs.

      • ST2094_10 will be written on each access unit as per constraint of section A.2.1 ts_103572v010101p.pdf.

      • ST2094_40 will be written on IDRs, and whenever the user changes its content, according to the persistency specification in A341S34-1-582r4-A341-Amendment-2094-40.pdf

Adaptive Bitrate Scaler

For streaming applications, video is distributed in different resolutions and bit rates to adapt to varying network bandwidth conditions. All adaptive bitrate (ABR) transcoding systems require an ABR scaler that downscales an input video stream to several different smaller resolutions that are then re-encoded. These smaller resolutions are referred to as an image pyramid or an ABR ladder.

The MA35D ABR scaler is an accelerator capable of generating up to 16 lower resolution output images from a single input image. The ABR scaler supports the following features:

  • Supports up to 12 taps in both horizontal and vertical direction per stage

  • High quality polyphase scaling with 64 phases and up to 12 taps in both horizontal and vertical direction per stage

  • Supports 8 and 10-bit 4:2:0

  • Luma and Chroma processed in parallel

  • Supports resolutions from 128x128 to 3840x2160, in multiples of 4

  • The scaler is tuned for downscaling and expects non-increasing resolutions in an ABR ladder. Increasing resolutions between outputs is supported but will reduce video quality.

Video Quality

The MA35D card nominally produces video quality (VQ) that is closely correlated to x264 medium, x265 medium and x265 slow presets, with respect to its accelerated AVC, HEVC and AV1 encoders. Furthermore, in case of AV1 encoders, -type-1 AV1 matches a similar VQ as x265 slow; whereas, -type-2 that of x265 medium. This video quality is highly dependent on video content so actual results may vary.

Performance Tables

The video processing power of the MA35D cards can be harnessed in many different ways, from running a few high-definition jobs to running many low-resolution ones, with or without scaling. The tables below show how many jobs can be run at real-time speed based on the use case and the number of cards available. All these configurations have been tested and validated by AMD and assume normal operating ranges.

Note

  1. In the following tables, density numbers linearly scale to up to 16 devices.

  2. It is assumed that per device, host chassis has set aside 8 hyper-threaded cores with 12GB of RAM.

Note

To meet the following density numbers for 30 FPS pipelines, it is recommended to decrease LA depth incrementally, until target density objectives are met. Refer to Automatic Look Ahead Depth Calculation for valid range of LA depth.

The following tables present density numbers for typical video renditions. However, it should be noted that encode capability of each engine, 4 per device, is best described as aggregated 4kp60. This, among other things, implies that densities of 4x1080p60 or rate of 1x1080p240 can be achieved. The latter implies that a 1080p60 VOD asset can be encoded at 4 times the speed. Furthermore, speed up rate holds linearly for renditions down to 540p30. To encode two Faster Than Real Time (FTRT) jobs on a single device, each job must be assigned to a dedicated slice. See -slice for details.

In tables, below, Single Density refers to any combination of AVC, HEVC or AV1 Type-2 encoders, whereas, Double Density refers to any combination of AVC, HEVC or AV1 Type-2 encoders along with AV1 Type-1 encoder.

It is noted that with respect to Transcode with Scale Jobs Tables, below, the output of a decoder can be split and encoded with any combination of AMA encoders. This in turn implies that the expected density numbers can vary from reported Single Density to Double Density, depending on encoder selection, for each output of the scaler.

To fully utilize all devices on a card and reach the stated densities, device selection needs to be explicitly done in a command line. See -hwaccel and Using Explicit Device IDs for more details.

Performance Tables for 8-bit Color

Number of Real-Time Transcode Jobs per Card (8-bit)

Transcode Use Case

Single Density

Double Density

4kp60

4

8

4kp30

8

16

1080p60

16

32

1080p30

32

64

720p60

32

64

720p30

68

136
Number of Real-Time Transcode with Scale Jobs per Card (8-bit)

Transcode with Scale Use Case

Single Density

Double Density

4kp60 to 1440p60

4

8

4kp30 to 1440p30

8

16

1080p60 to 720p60

16

32

1080p30 to 720p30

32

64

720p60 to 540p60

32

64

720p30 to 540p30

68

136
Number of Real-Time ABR Ladders (8-bit)

ABR Ladders Use Case

1 Card

2160p60 to 1440p60, 1080p60, 720p30, 480p30, 360p30, 240p30, 144p30

4

2160p30 to 2160p30, 1440p30, 1080p30, 720p30, 480p30, 360p30, 240p30, 144p30

4

1080p60 to 1080p60, 720p60, 720p30, 480p30, 360p30, 160p30

8

1080p60 to 720p60, 720p30, 480p30, 360p30, 160p30

16

1080p30 to 1080p30, 720p30, 480p30, 240p30

16

720p30 to 720p30, 480p30, 240p30

40

Performance Tables for 10-bit Color

Number of Real-Time Transcode Jobs per Card (10-bit)

Transcode Use Case

Single Density

Double Density

4kp60

4

8

4kp30

8

16

1080p60

16

32

1080p30

32

64

720p60

32

64

720p30

68

136
Number of Real-Time Transcode with Scale Jobs per Card (10-bit)

Transcode with Scale Use Case

Single Density

Double Density

4kp60 to 1440p60

4

8

4kp30 to 1440p30

8

16

1080p60 to 720p60

16

32

1080p30 to 720p30

32

64

720p60 to 540p60

32

64

720p30 to 540p30

68

136
Number of Real-Time ABR Ladders (10-bit)

ABR Ladders Use Case

1 Card

2160p60 to 1440p60, 1080p60, 720p30, 480p30, 360p30, 240p30, 144p30

4

2160p30 to 2160p30, 1440p30, 1080p30, 720p30, 480p30, 360p30, 240p30, 144p30

4

1080p60 to 1080p60, 720p60, 720p30, 480p30, 360p30, 160p30

8

1080p60 to 720p60, 720p30, 480p30, 360p30, 160p30

16

1080p30 to 1080p30, 720p30, 480p30, 240p30

16

720p30 to 720p30, 480p30, 240p30

40